Automatic Design of VLIW and EPIC Instruction Formats

instruction format design, template design, instruction-set architecture, abstract ISA, concrete ISA, VLIW processors, EPIC processors, HPL-PD architecture, instruction encoding, bit allocation, affinity allocation, applicationspecific processors, design space exploration Very long instruction word (VLIW), and in its generalization, explicitly parallel instruction computing (EPIC) architectures explicitly encode multiple independent operations within each instruction. The processor's instruction-set architecture (ISA) specifies the interface between hardware and software, while its instruction format specifies the precise syntax and binary encodings of all instructions in the ISA. A designer of instruction formats must make efficient use of the available hardware resources and make intelligent trade-offs between decoder complexity and instruction width. Simple encodings lead to faster and less expensive decode hardware, but increase instruction width. Wider instruction formats lead to increased code size and more expensive instruction caches and instruction data paths. In embedded systems, code size is often a major component of total system cost, since the program is stored in ROM. In this report, we present an algorithmic approach to automatic design of high-quality VLIW/EPIC instruction formats. Our design process can be used to explore a large design space to find good designs at varying cost-performance points. This is also essential for automated design-space exploration of application-specific VLIW/EPIC processors.